storage-out bus(of memory),output bus

74mw, by applying master-slave column amplifier and the technology of pided-output-bus, which reduced more than 80%.

采用新型的主从两级放大的列读出结构和输出总线分割技术相结合。

For the readout rate of 4MHz, by using the output bus pre-settling and the stand-by low power donsumption,the power consumption of this design is reduced from 8.

当读出频率为4MHz时,通过采用输出总线预置技术和stand-by低功耗策略,与主从两级放大的列读出级相比,功耗从8。